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    Wyświetlanie 1-9 z 9
    Tytuł:
    Improving the LUT count for Mealy FSMs with transformation of output collections
    Autorzy:
    Barkalov, Alexander
    Titarenko, Larysa
    Mazurkiewicz, Małgorzata
    Tematy:
    Mealy FSM
    FPGA
    LUT
    state code
    FSM
    kod stanu
    Pokaż więcej
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Powiązania:
    https://bibliotekanauki.pl/articles/2172120.pdf  Link otwiera się w nowym oknie
    Opis:
    A method is proposed which aims at reducing the number of LUTs in the circuits of FPGA-based Mealy finite state machines (FSMs) with transformation of collections of outputs into state codes. The reduction is achieved due to the use of two-component state codes. Such an approach allows reducing the number of state variables compared with FSMs based on extended codes. There are exactly three levels of LUTs in the resulting FSM circuit. Each partial function is represented by a single-LUT circuit. The proposed method is illustrated with an example of synthesis. The experiments were conducted using standard benchmarks. They show that the proposed method produces FSM circuits with significantly smaller LUT counts compared with those produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of output collection codes into extended state codes). The LUT count is decreased by, on average, from 9.86% to 59.64%. The improvement of the LUT count is accompanied by a slightly improved performance. The maximum operating frequency is increased, on average, from 2.74% to 12.93%. The advantages of the proposed method become more pronounced with increasing values of FSM inputs and state variables.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Reducing the number of LUTs for Mealy FSMs with state transformation
    Autorzy:
    Barkalov, Alexander
    Titarenko, Larysa
    Mielcarek, Kamil
    Tematy:
    Mealy FSM
    FPGA
    LUT
    extended state code
    combined state code
    FSM
    kod stanu
    Pokaż więcej
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Powiązania:
    https://bibliotekanauki.pl/articles/59123839.pdf  Link otwiera się w nowym oknie
    Opis:
    In many digital systems, various sequential blocks are used. This paper is devoted to the case where the model of a Mealy finite state machine (FSM) represents the behaviour of a sequential block. The chip area occupied by an FSM circuit is one of the most important characteristics used in logic synthesis. In this paper, a method is proposed which aims at reducing LUT counts for FPGA-based Mealy FSMs with transformation of state codes into FSM outputs. This is done using the combined state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed method leads to LUT-based Mealy FSM circuits having exactly three levels of logic blocks. Under certain conditions, each function for any logic level is represented by a circuit including a single LUT. The proposed approach is illustrated with an example of synthesis. The results of experiments conducted using standard benchmarks show that the proposed method produces LUT-based FSM circuits with significantly smaller LUT counts than is the case for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, and transformation of binary codes into extended state codes). The LUT count is decreased by an average of 17.96 to 91.8%. Moreover, if some conditions are met, the decrease in the LUT count is accompanied with a slight improvement in the operating frequency compared with circuits based on extended state codes. The advantages of the proposed method multiply with increasing the numbers of FSM inputs and states.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Synteza automatu Moore’a z wbudowanym blokiem pamięci w strukturach programowalnych
    EMB-based synthesis of Moore FSM
    Autorzy:
    Kołopieńczyk, M.
    Barkalov, A.
    Titarenko, L.
    Tematy:
    Moore FSM
    RAM
    wbudowane bloki pamięci
    projektowanie
    układy logiczne
    Mealy FSM
    FPGA
    Embedded Memory Block
    design
    logic circuit
    Pokaż więcej
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Powiązania:
    https://bibliotekanauki.pl/articles/972136.pdf  Link otwiera się w nowym oknie
    Opis:
    W artykule zostanie przedstawiona metoda umożliwiająca syntezę skończonego automatu stanów typu Moore’a z wbudowanym blokiem pamięci (ang. Embedded Memory Blocks, EMB) w strukturach programowalnych typu FPGA (ang. Field Programmable Gate Array, FPGA). Zaproponowana metoda bazuje na kodowaniu pewnej wybranej części zbioru warunków logicznych przez dodatkowe zmienne. W artykule zostanie zaprezentowany przykład projektowania układu.
    The model of the Moore finite state machine (FSM) is very often used for representing a control unit [1]. Nowadays, two classes of programmable logic devices: complex programmable logic devices (CPLD) and field-programmable gate arrays (FPGA) are used for implementing logic circuits of FSMs [2, 3]. This paper deals with FPGA-based Moore FSMs. It is very important to use EMBs in the logic design. It leads to decreasing in both the number of interconnections and chip area occupied by an FSM logic circuit. In turn, it results in decrease in the propagation time as well as the consumed power of a circuit [9]. A lot of methods for implementing an FSM logic circuit with RAMs are known [10 – 19]. For rather complex FSMs, the method of replacement of logical conditions [20] is used. In this case, optimization efforts target hardware reduction for the multiplexer executing the replacement. In this paper we propose a method based on existence of pseudoequivalent states of the Moore FSM for solving this problem [21]. The method is based on replacement of some part of the set of logical conditions by additional variables. It results in diminishing the number of LUTs in the multiplexer used for replacement of logical conditions. To represent a control algorithm, the language of graph-schemes of algorithms [20] is used. An example of application of the proposed design method is given.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Improving characteristics of LUT-based Mealy FSMs
    Autorzy:
    Barkalov, Alexander
    Titarenko, Larysa
    Mielcarek, Kamil
    Tematy:
    FPGA
    LUT
    Mealy FSM
    structural decomposition
    two fold state assignment
    energy consumption
    FSM
    dekompozycja strukturalna
    zużycie energii
    Pokaż więcej
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Powiązania:
    https://bibliotekanauki.pl/articles/1838158.pdf  Link otwiera się w nowym oknie
    Opis:
    Practically, any digital system includes sequential blocks represented using a model of finite state machine (FSM). It is very important to improve such FSM characteristics as the number of logic elements used, operating frequency and consumed energy. The paper proposes a novel technology-dependent design method targeting a decrease in the number of look-up table (LUT) elements and their levels in logic circuits of FPGA-based Mealy FSMs. It produces FSM circuits having three levels of logic blocks. Also, it produces circuits with regular systems of interconnections between the levels of logic. The method is based on dividing the set of internal states into two subsets. Each subset corresponds to a unique part of an FSM circuit. Only a single LUT is required for implementing each function generated by the first part of the circuit. The second part is represented by a multi-level circuit. The proposed method belongs to the group of two-fold state assignment methods. Each internal state is encoded as an element of the set of states and as an element of some of its subsets. A binary state assignment is used for states corresponding to the first part of the FSM circuit. The one-hot assignment is used for states corresponding to the second part. An example of FSM synthesis with the proposed method is shown. The experiments with standard benchmarks are conducted to analyze the efficiency of the proposed method. The results of experiments show that the proposed approach leads to diminishing the number of LUTs in the circuits of rather complex Mealy FSMs having more than 15 internal states. The positive property of this method is a reduction in energy consumption (without any overhead cost) and an increase in operating frequency compared with other investigated methods.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Statechart-based Controllers Synthesis in FPGA Structures with Embedded Array Blocks
    Autorzy:
    Łabiak, G.
    Borowik, G.
    Tematy:
    digital controller
    statechart
    FSM
    decomposition
    FPGA
    symbolic methods
    embedded memory
    Pokaż więcej
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Powiązania:
    https://bibliotekanauki.pl/articles/226148.pdf  Link otwiera się w nowym oknie
    Opis:
    Statechart diagrams, in general, are visual formalism for description of complex systems behaiour. Digital controllers, which act as reactive systems, can be very conveniently modeled with statecharts and efficiently synthesized in modern programmable devices. The paper presents in details syntax and semantics of statecharts and new implementation scheme. The issue of statecharts synthesis is not still ultimately solved. Main feature of the presented approach is the transformation of statechart diagrams into Finite State Machine, and through KISS format, functional decomposition and mapping into Embedded Memory Blocks. Embedded Memory are part of the modern programmable devices.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Algorytm funkcjonalnej dekompozycji symbolicznej automatów skończonych dla celów implementacji w strukturach FPGA
    Symbolic Functional Decomposition Algorithm for FSM Implementation in FPGA Structures
    Autorzy:
    Szotkowski, P.
    Rawski, M.
    Tematy:
    funkcjonalna dekompozycja symboliczna
    automat skończony
    FSM
    FPGA
    symbolic functional decomposition
    finite state machine
    Pokaż więcej
    Wydawca:
    Stowarzyszenie Inżynierów i Techników Mechaników Polskich
    Powiązania:
    https://bibliotekanauki.pl/articles/155717.pdf  Link otwiera się w nowym oknie
    Opis:
    Dotychczasowe podejście do implementacji automatów skończonych w układach FPGA składa sie z dwóch etapów: kodowania stanów automatu oraz mapowania powstałych funkcji w strukturze układu. W przypadku mapowania za pomocą dekompozycji funkcjonalnej trudno jest znaleźć "dobrą" metodę kodowania stanów, szczególnie przy zastosowaniu proce-su syntezy wielopoziomowej. Artykuł opisuje algorytm funkcjonalnej dekompozycji symbolicznej, który zamiast osobnego etapu kodowania wprowadza sukcesywne kodowanie stanów gwarantujące dobrą jakość dekompozycji, oraz przedstawia działanie tego algorytmu na przykładzie wybranego automatu skończonego.
    The following paper presents an algorithm of symbolic functional decomposition for implementation of finite state machines in FPGA circuits. The idea of symbolic functional decomposition does not require a separate step of encoding the FSM's states. This method uses a description of the FSM that maintains a symbolic representation of the machine's states and introduces their encoding gradually, during each of the iterations of the decomopsition process; such approach guarantees high quality of the final decomposition. This paper presents an algorithm of symbolic functional decomposition based on blanket algebra. Each of the algorithm's steps is described in detail, as well as presented on an example FSM.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Hardware reduction for LUT-based mealy FSMs
    Autorzy:
    Barkalov, A.
    Titarenko, L.
    Mielcarek, K.
    Tematy:
    Mealy FSM
    FPGA
    LUT
    partition
    encoding collection
    output variables
    automat Mealy'ego
    zbiór kodowany
    zmienne wyjściowe
    Pokaż więcej
    Wydawca:
    Uniwersytet Zielonogórski. Oficyna Wydawnicza
    Powiązania:
    https://bibliotekanauki.pl/articles/331362.pdf  Link otwiera się w nowym oknie
    Opis:
    A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each state has two codes. It diminishes the number of arguments in input memory functions. An example of synthesis is given, along with results of investigations. The method targets rather complex FSMs, having more than 15 states.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Improving LUT count of FPGA-based sequential blocks
    Autorzy:
    Barkalov, Alexander
    Titarenko, Larysa
    Mazurkiewicz, Małgorzata
    Krzywicki, Kazimierz
    Tematy:
    FPGA
    LUT
    Mealy FSM
    synthesis
    structural decomposition
    product terms
    partition
    automat Mealy'ego
    synteza
    rozkład strukturalny
    warunki produktu
    przegroda
    Pokaż więcej
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Powiązania:
    https://bibliotekanauki.pl/articles/2173598.pdf  Link otwiera się w nowym oknie
    Opis:
    Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
    Tytuł:
    Improving LUT count of FPGA-based sequential blocks
    Autorzy:
    Barkalov, Alexander
    Titarenko, Larysa
    Mazurkiewicz, Małgorzata
    Krzywicki, Kazimierz
    Tematy:
    FPGA
    LUT
    Mealy FSM
    synthesis
    structural decomposition
    product terms
    partition
    automat Mealy'ego
    synteza
    rozkład strukturalny
    warunki produktu
    przegroda
    Pokaż więcej
    Wydawca:
    Polska Akademia Nauk. Czytelnia Czasopism PAN
    Powiązania:
    https://bibliotekanauki.pl/articles/2090732.pdf  Link otwiera się w nowym oknie
    Opis:
    Very often, a digital system includes sequential blocks which can be represented using a model of the finite state machine (FSM). It is very important to improve such FSM characteristics as the number of used logic elements, operating frequency and consumed energy. The paper proposes a novel technology-dependant design method targeting LUT-based Mealy FSMs. It belongs to the group of structural decomposition methods. The method is based on encoding the product terms of Boolean functions representing the FSM circuit. To diminish the number of LUTs, a partition of the set of internal states is constructed. It leads to three-level logic circuits of Mealy FSMs. Each function from the first level requires only a single LUT to be implemented. The method of constructing the partition with the minimum amount of classes is proposed. There is given an example of FSM synthesis with the proposed method. The experiments with standard benchmarks were conducted. They show that the proposed method can improve such FSM characteristics as the number of used LUTs. This improvement is accompanied by a decrease in performance. A positive side effect of the proposed method is a reduction in power consumption compared with FSMs obtained with other design methods.
    Dostawca treści:
    Biblioteka Nauki
    Artykuł
      Wyświetlanie 1-9 z 9

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