Temat: GATE - Prolib Integro

Skocz do pozycji: 1.

Tytuł:: Projekt i implementacja sterowników karty graficznej VGA w układach FPGA
Design and implementation of VGA graphics card in FPGA technology
Autorzy:: Niemojewski, M.
Sapiecha, P.
Tematy:: VGA
Video Graphics Adapter
FPGA
field-programmable gate array
Altera
Stratix II
Lancelot VGA
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/155616.pdf Link otwiera się w nowym oknie
Opis:: Celem pracy jest zaprojektowanie interfejsu graficznego i tekstowego umożliwiającego prezentacje informacji na ekranie monitora VGA wykorzystując technologie logicznych układów programowalnych, napisanie sterowników sprzętu dla systemu operacyjnego žClinux oraz przeprowadzenie i analiza wyników testów uzyskanego rozwiązania ze względu na parametry: prędkość rysowania obrazu, stopień obciążenia pamięci.
The paper presents design and implementation of the text and graphics interface for FPGA based system. The article describes VHDL module and video graphics driver for žClinux operating system. The article describes tests of the device. The paper presents possible future work for the design.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Calibration of a mixed-signal power network transient stability analysis emulator
Autorzy:: Lanz, G
Fabre, L.
Lilis, G
Kyriakidis, T
Sallin, D
Cherkaoui, R.
Kayal, M.
Tematy:: analog computer
calibration
field programmable gate array (FPGA)
FPGA
mixed signal
power system dynamics
komputer analogowy
kalibracja
field-programmable gate array
sygnał mieszany
dynamika systemu elektroenergetycznego; Pokaż więcej
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Powiązania:: https://bibliotekanauki.pl/articles/398094.pdf Link otwiera się w nowym oknie
Opis:: The emerging ﬁeld of power system emulation for real time smart grid management is very demanding in terms of speed and accuracy. This paper provides detailed information about the electronics calibration process of a high-speed power network emulator dedicated to the transient stability analysis of power systems. This emulator uses mixed-signal hardware to model the dynamic behavior of a power network. Special design allows the self-calibration of the analog electronics through successive measurements and correction steps. The calibration operation guarantees high resolution of the transient stability analysis results, so that they can be reliably used for operational planning and control on real power networks.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Polyphase Comb Filter Based on Dispatching Input Bit-stream and Interlaying Multiplexer Techniques for Sigma-Delta ADCs
Autorzy:: Abdollahvand, S.
Goes, J.
Paulino, N.
Gomes, L.
Tematy:: filtr decymacyjny
filtr wielofazowy
modulator sigma-delta
field-programmable gate array
FPGA
decimation filter
Polyphase Comb filter
sigma-delta modulators
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Powiązania:: https://bibliotekanauki.pl/articles/397961.pdf Link otwiera się w nowym oknie
Opis:: This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: FPGA implementations of low precision floating point multiply-accumulate
Autorzy:: Amaricai, A.
Boncalo, O.
Sicoe, O
Tematy:: digital arithmetic
floating point arithmetic
FPGA
field programmable gate array (FPGA)
multiply-accumulate
dot product
arytmetyka cyfrowa
arytmetyka zmiennoprzecinkowa
field-programmable gate array
MAC
iloczyn skalarny; Pokaż więcej
Wydawca:: Politechnika Łódzka. Wydział Mikroelektroniki i Informatyki
Powiązania:: https://bibliotekanauki.pl/articles/397897.pdf Link otwiera się w nowym oknie
Opis:: Floating point (FP) multiply-accumulate (MAC) represents one of the most important operations in a wide range of applications, such as DSP, multimedia or graphic processing. This paper presents a FP MAC half precision (16-bit) FPGA implementation. The main contribution of this work is represented by the utilization of modern FPGA DSP block for performing both mantissa multiplication and mantissa accumulation. In order to use the DSP block for these operations, the alignment right shifts are performed before the multiply-add stage: a right shift on one of the multiplicand, and, a left shift for the other. This results in efficient DSP usage; thus both cost savings and higher performance (high working frequencies and low latencies) are targeted for MAC operations.
Dostawca treści:: Biblioteka Nauki

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na półce

Skocz do pozycji: 5.

Tytuł:: Firmware development for the fibre-optic seismometer based on FOG
Autorzy:: Kamiński, Marek
Tylman, Wojciech
Jabłoński, Grzegorz
Kotas, Rafał
Amrozik, Piotr
Sakowicz, Bartosz
Jaroszewicz, Leszek R.
Tematy:: fibre-optic rotational seismometer
Sagnac effect
simulation environment
field-programmable gate array
high-level synthesis; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Stowarzyszenie Elektryków Polskich
Powiązania:: https://bibliotekanauki.pl/articles/59112948.pdf Link otwiera się w nowym oknie
Opis:: The main goal of the article is to present the concept of using a simulation environment when designing an advanced fibre-optic seismometer (FOS) using a field-programmable gate array (FPGA) computing system. The first part of the article presents the advanced requirements regarding the FOS principle of operation, as well as the measurement method using a closed-loop operation. The closed-loop control algorithm is developed using the high-level language C++ and then it is synthesised into an FPGA. The following part of the article describes the simulation environment developed to test the operation of the control algorithm. The environment includes a model of components of the measurement system, delays, and distortions in the signal processing path, and some of the measurement system surroundings. The article ends with a comparison of simulation data with measurements. The obtained results are consistent and prove correctness of the methodology adopted by the authors.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 6.

Tytuł:: Employing FPGA DSP blocks for time-to-digital conversion
Autorzy:: Kwiatkowski, Paweł
Tematy:: time-to-digital converter
time coding line
time interval counter
digital signal processing
field-programmable gate array; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/221505.pdf Link otwiera się w nowym oknie
Opis:: The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in comparison with the common conversion method (carry chain-based time coding line). Two TDCs are presented and tested depending on DSP configuration. The converters were implemented in a Kintex-7 FPGA device manufactured by Xilinx in 28 nm CMOS process. The tests performed show possibilities to obtain mean resolution of 4.2 ps but measurement precision is limited to at most 15 ps mainly due to high conversion nonlinearities. The presented solution saves FPGA programmable logic blocks and has an advantage of a wider operation range when compared with a carry chain-based time coding line.
Dostawca treści:: Biblioteka Nauki

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na półce

Skocz do pozycji: 7.

Tytuł:: A time-domain pulse amplitude and width discrimination method for photon counting
Autorzy:: del Mar Correa, M.
Pérez, F. R.
Tematy:: field-programmable gate array
time-to-digital converter
spectroscopy
photomultiplier
photon counting
discriminator
after-pulsing
low-voltage differential signalling; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/220971.pdf Link otwiera się w nowym oknie
Opis:: This work shows a time-domain method for the discrimination and digitization of parameters of voltage pulses coming from optical detectors, taking into account the presence of electronic noise and afterpulsing. Our scheme is based on an FPGA-based time-to-digital converter as well as an adjustable-threshold comparator complemented with commercial elements. Here, the design, implementation and optimization of a multiphase TDC using delay lines shorter than a single clock period is also described. The performance of this signal processing system is discussed through the results from the statistical code density test, statistical distributions of measurements and information gathered from an optical detector. Unlike dual voltage threshold discriminators or constant-fraction discriminators, the proposed method uses amplitude and time information to define an adjustable discrimination window that enables the acquisition of spectra.
Dostawca treści:: Biblioteka Nauki

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na półce

Skocz do pozycji: 8.

Tytuł:: FPGA implementation of logarithmic versions of Baum-Welch and Viterbi algorithms for reduced precision hidden Markov models
Autorzy:: Pietras, M.
Klęsk, P.
Tematy:: hidden Markov models
numerical stability
Viterbi algorithm
parallel architecture
field-programmable gate array
ukryte modele Markowa
stabilność numeryczna
Algorytm Viterbiego
architektura równoległa; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/201874.pdf Link otwiera się w nowym oknie
Opis:: This paper presents a programmable system-on-chip implementation to be used for acceleration of computations within hidden Markov models. The high level synthesis (HLS) and “divide-and-conquer” approaches are presented for parallelization of Baum-Welch and Viterbi algorithms. To avoid arithmetic underflows, all computations are performed within the logarithmic space. Additionally, in order to carry out computations efficiently – i.e. directly in an FPGA system or a processor cache – we postulate to reduce the floating-point representations of HMMs. We state and prove a lemma about the length of numerically unsafe sequences for such reduced precision models. Finally, special attention is devoted to the design of a multiple logarithm and exponent approximation unit (MLEAU). Using associative mapping, this unit allows for simultaneous conversions of multiple values and thereby compensates for computational efforts of logarithmic-space operations. Design evaluation reveals absolute stall delay occurring by multiple hardware conversions to logarithms and to exponents, and furthermore the experiments evaluation reveals HMMs computation boundaries related to their probabilities and floating-point representation. The performance differences at each stage of computation are summarized in performance comparison between hardware acceleration using MLEAU and typical software implementation on an ARM or Intel processor.
Dostawca treści:: Biblioteka Nauki

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