Temat: implementation - Prolib Integro

Skocz do pozycji: 1.

Tytuł:: Some Schemes for Implementation of Arithmetic Operations with Complex Numbers Using Squaring Units
Autorzy:: Cariow, A.
Cariowa, G.
Tematy:: complex number arithmetic
squaring unit
implementation complexity reduction
hardware implementation; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/114347.pdf Link otwiera się w nowym oknie
Opis:: In this paper, new schemes for a squarer, multiplier and divider of complex numbers are proposed. Traditional structural solutions for each of these operations require the presence of some number of general-purpose binary multipliers. The advantage of our solutions is a removing of multiplications through replacing them by less costly squarers. We use Logan's trick and quarter square technique, which propose to replace the calculation of the product of two real numbers by summing the squares. Replacing usual multipliers with digital squares implies the reducing power consumption as well as decreases the complexity of the hardware circuit. The squarer requiring less area and power as compared to general-purpose multiplier, it is interesting to assess the use of squarers to implementation of complex arithmetic.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Hardware implementation of parametric algorithm for asynchronously gathered measurement data based on the FPGA technology
Autorzy:: Janowski, T.
Szworski, K.
Zając, R.
Tematy:: hardware implementation
FPGA technology
hydroacoustic system; Pokaż więcej
Wydawca:: Polskie Towarzystwo Akustyczne
Powiązania:: https://bibliotekanauki.pl/articles/332532.pdf Link otwiera się w nowym oknie
Opis:: The hydroacoustic system based on DOA estimation utilizes passive antenna composed of many hydrophones. The samples of the arriving acoustic signal must be gathered synchronously from each hydrophone. This enables to take advantage of parametric processing signals methods. These methods make possible determination of the amplitude and the phase relationship among particular hydrophones. The newest complex systems made up of many sub modules uses network solutions. In the case of Ethernet network some standards (e.g. Precision Time Protocol) are defined to enable synchronization of the data (samples) gathered from many hydrophones by the clock synchronization. When the antenna consists of few hydrophones then the special concentrator connected point-to-point to hydrophones can be utilized. This article discusses the issue related to PTP as well as concentrator based on FPGA technology, which uses simple UDP protocol. In the case of concentrator the synchronous method of the I/Q detection which not requires synchronous samples acquisition is also presented.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 3.

Tytuł:: Implementacja standardu szyfrowania AES w układzie FPGA dla potrzeb sprzętowej akceleracji obliczeń
The AES ciper standard implementation on FPGA for hardware accelerated computing
Autorzy:: Gielata, A.
Russek, P.
Wiatr, K.
Tematy:: Rijndael
AES
implementacja sprzętowa
FPGA
hardware implementation; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/152602.pdf Link otwiera się w nowym oknie
Opis:: Tematem artykułu jest implementacja standardu szyfrowania danych AES-128 w układach reprogramowalnych FPGA. W systemach, gdzie wymagana jest duża szybkość szyfrowania informacji implementacje programowe okazują się zbyt wolne. W związku z tym zachodzi konieczność sprzętowej akceleracji obliczeń, a idealnym rozwiązaniem jest wykorzystanie do tego celu możliwości, jakie dają układy reprogramowalne FPGA. Do implementacji w języku VHDL wybrana została podstawowa wersja algorytmu określonego w standardzie AES. W celu uzyskania maksymalnej szybkości szyfrowania zastosowana została architektura potokowa modułu.
In this paper we investigate hardware implementation of AES-128 cipher standard on FPGA technology. In many network applications software implementations of cryptographic algorithms are slow and inefficient. To solve the problems custom architecture in reconfigurable hardware was used to speed up the performance and flexibility of Rijndael algorithm implementation. We aimed at achieving the maximum speed and efficiency of cipher process, therefore pipeline architecture of AES module was proposed. The investigations involved simulations and synthesis of VHDL code utilizing Virtex4 series of Xilinx.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: High-performance FPGA Architecture for Data Streams Processing on Example of IPsec Gateway
Autorzy:: Korona, M.
Skowron, K.
Trzepinski, M.
Rawski, M.
Tematy:: IPsec
FPGA
hardware implementation
data stream processing; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/227331.pdf Link otwiera się w nowym oknie
Opis:: In modern digital world, there is a strong demand for efficient data streams processing methods. One of application areas is cybersecurity - IPsec is a suite of protocols that adds security to communication at the IP level. This paper presents principles of high-performance FPGA architecture for data streams processing on example of IPsec gateway implementation. Efficiency of the proposed solution allows to use it in networks with data rates of several Gbit/s.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Hardware implementation of a decision tree classifier for object recognition applications
Autorzy:: Fularz, M.
Kraft, M.
Tematy:: decision tree
hardware implementation
FPGA
object recognition; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/114595.pdf Link otwiera się w nowym oknie
Opis:: Hardware implementation of a widely used decision tree classifier is presented in this paper. The classifier task is to perform image-based object classification. The performance evaluation of the implemented architecture in terms of resource utilization and processing speed are reported. The presented architecture is compact, flexible and highly scalable and compares favorably to software-only solutions in terms of processing speed and power consumption.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 6.

Tytuł:: Low-cost hardware implementations of Salsa20 stream cipher in programmable devices
Autorzy:: Sugier, J.
Tematy:: FPGA
stream cipher
hardware implementation
pipelining
iterative architecture; Pokaż więcej
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Powiązania:: https://bibliotekanauki.pl/articles/2069359.pdf Link otwiera się w nowym oknie
Opis:: Salsa20 is a 256-bit stream cipher that has been proposed to eSTREAM, ECRYPT Stream Cipher Project, and is considered to be one of the most secure and relatively fastest proposals. This paper describes hardware implementation of various architectures of this cipher in popular Field Programmable Gate Arrays (FPGA). The implemented architectures are based on the loop-unrolled data flow organization and after pipelining they can reach the throughput in the range of 20 – 30 Gbps even after fully automatic implementation in popular low-cost families of Spartan-3 and Spartan-6 from Xilinx. More resource-limited iterative architectures achieve speed of 1 – 2 Gbps. The results that are included in this work present potential of the algorithm when it is implemented in a specific FPGA environment and provide some information for evaluation of cipher effectiveness in contemporary popular programmable devices.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 7.

Tytuł:: Faster Point Scalar Multiplication on Short Weierstrass Elliptic Curves over Fp using Twisted Hessian Curves over Fp2
Autorzy:: Wroński, M.
Tematy:: elliptic curve cryptography
hardware implementation
twisted Hessian curves; Pokaż więcej
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Powiązania:: https://bibliotekanauki.pl/articles/308416.pdf Link otwiera się w nowym oknie
Opis:: This article shows how to use fast F_p2 arithmetic and twisted Hessian curves to obtain faster point scalar multiplication on elliptic curve E_SW in short Weierstrass form over F_p. It is assumed that p and #E_SW(F_p) are different large primes, #E(F_q) denotes number of points on curve E over field F_q and #E^t _SW (F_p), where E^t is twist of E, is divisible by 3. For example this method is suitable for two NIST curves over F_p: NIST P-224 and NIST P-256. The presented solution may be much faster than classic approach. Presented solution should also be resistant for side channel attacks and information about Y coordinate should not be lost (using for example Brier-Joye ladder such information may be lost). If coefficient A in equation of curve E_SW : y² =x³+Ax+B in short Weierstrass curve is not of special form, presented solution is up to 30% faster than classic approach. If A=−3, proposed method may be up to 24% faster.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 8.

Tytuł:: Design and implementation of improved sliding mode controller on 6R manipulator
Autorzy:: Korayem, M. H.
Nekoo, S. R.
Khademi, A.
Abdollahi, F.
Tematy:: improved sliding mode control
chattering
DLCC
hardware implementation; Pokaż więcej
Wydawca:: Polskie Towarzystwo Mechaniki Teoretycznej i Stosowanej
Powiązania:: https://bibliotekanauki.pl/articles/280702.pdf Link otwiera się w nowym oknie
Opis:: In this work, we present an improved sliding mode control (ISMC) technique designed and implemented for control of 6R manipulator. Sliding mode control (SMC) is a well-known nonlinear robust method for controlling systems in the presence of uncertainties and disturbances and systems with complex dynamics as in manipulators. Despite this good property, it is difficult to implement this method for the manipulator with a complex structure and more than three degree-of-freedom because of the complicated and massive equation and chattering phenomenon as a property of SMC in control inputs. Here, the chattering phenomenon is eliminated by using an effective algorithm called ISMC and implemented to 6R manipulator by using a low-cost control board based on an ARM microcontroller with high accuracy and memory. The carrying load is considered as the uncertainty for the manipulator, while the dynamic load carrying capacity (DLCC) is considered as a robot performance criterion showing robustness of the controller. The results of simulations and experiments show that the proposed approach has a good performance and is suitable and practical to be applied for manipulators.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 9.

Tytuł:: Hardware implementation of the Hough Techniques for Irregular Colour and Grey-level Pattern Recognition
Autorzy:: Żorski, W.
Żak, A.
Turner, M.
Tematy:: Hough transform
computer vision
hardware implementation
irregular patterns; Pokaż więcej
Wydawca:: Wojskowa Akademia Techniczna im. Jarosława Dąbrowskiego
Powiązania:: https://bibliotekanauki.pl/articles/273196.pdf Link otwiera się w nowym oknie
Opis:: This paper presents a hardware implementation of the Hough technique applied to the tasks of irregular colour and grey-level pattern recognition. The presented method is based on the Hough Transform with a parameter space defined by translation, rotation and scaling operations. An essential element of this method is the generalisation of the Hough Transform for grey level and colour images. The technique simplifies the application of the Hough Transform to irregular patterns recognition tasks. The hardware implementation accelerates the calculations considerably and may be used in computer vision systems, for example, in a robotic system.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 10.

Tytuł:: Efficiency of Spartan-7 FPGA devices in implementation of contemporary cryptographic algorithms
Autorzy:: Sugier, J.
Tematy:: hardware implementation
loop unrolling
pipelining
AES
BLAKE
KECCAK
SHA-3; Pokaż więcej
Wydawca:: Uniwersytet Morski w Gdyni. Polskie Towarzystwo Bezpieczeństwa i Niezawodności
Powiązania:: https://bibliotekanauki.pl/articles/2068736.pdf Link otwiera się w nowym oknie
Opis:: Hardware implementations of cryptographic algorithms are ubiquitous in contemporary computer systems where they are used to ensure appropriate level of security e.g. in high-speed data transmission, authentication and access control, distributed cloud storage, etc.. In this paper we evaluate size and speed efficiency of FPGA implementations of selected popular cryptographic algorithms in the newest cost-sensitive Spartan-7 devices form Xilinx, Inc.. The investigated set of algorithms included four examples: the AES-128 standard symmetric block cipher, the BLAKE-256 hash function and two size variants of the KECCAK-f[b] compression function, b = 400 and 1600, with the larger variant being used as the core of the new SHA-3 standard. The main aim of this research was to provide a uniform and comparable implementation approach for all the ciphers so that the new potentials of the Spartan-7 internal architecture would be put to the test in realization of their specific cryptographic transformations and data distribution. Each of the four algorithms was implemented in five architectures: the basic iterative one (with one instance of the cipher round instantiated in hardware) plus two loop unrolled ones (with two and four or five rounds in hardware) and their two pipelined variants (with registers at the outputs of each round enabling parallel processing of multiple streams of data). Uniform implementation methodology applied to 20 cases of cipher & architecture combinations created a consistent testbed, producing comparable results which allowed to evaluate efficiency of the new hardware platform in implementation of the different algorithms in various unrolled and pipelined organizations.
Dostawca treści:: Biblioteka Nauki

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