Temat: Mosfet - Prolib Integro

Skocz do pozycji: 1.

Tytuł:: Charge-pumping characterization of FILOX vertical MOSFETs
Autorzy:: Głuszko, G.
Łukasiak, L.
Ashburn, P.
Tematy:: charge-pumping
FILOX
interface traps
MOSFET
vertical MOSFET; Pokaż więcej
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Powiązania:: https://bibliotekanauki.pl/articles/308623.pdf Link otwiera się w nowym oknie
Opis:: This paper presents for the first time the results of charge-pumping (CP) measurements of FILOX vertical transistors. The aim of these measurements is to provide information on the density of interface traps at the Si-SiO2 interface fabricated in a non-standard process. Flat-band and threshold voltage, as well as density of interface traps are determined. Good agreement between threshold-voltage values obtained from CP and I-V measurements is observed.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Behavioral modeling of stressed MOSFET
Autorzy:: Gniazdowski, Zenon
Wydawca:: Warszawska Wyższa Szkoła Informatyki
Cytata wydawnicza:: Gniazdowski, Z. (2015). Behavioral modeling of stressed MOSFET. Zeszyty Naukowe WWSI, 9(13), 103-126.
Opis:: In this paper piezoconductivity phenomenon in MOSFET channel is discussed and extension of drain current model with possibility of stress consideration is proposed. Analysis of obtained model combined with examination of stress components inherent in the MOSFET channel as well as distributions of specific piezoconductance coefficients on a plane of channel can show which directions of transistor channel are desirable for improvement of MOSFET performances. This model gives possibility to predict optimal transistor channel orientation, for the given stress state in MOSFET channel. Possible simplification of this model is considered. In particular, stress state and significant piezoconductance coefficient distributions on planes {100}, {110} as well as {111} are analyzed. For assumed particular cases of stress state in the channel, final models of MOSFT for considered specific planes are given.
Dostawca treści:: Repozytorium Centrum Otwartej Nauki

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Skocz do pozycji: 3.

Tytuł:: Behavioral modeling of stressed MOSFET
Autorzy:: Gniazdowski, Z.
Tematy:: piezoconductivity
stressed MOSFET
strained silicon
MOSFET model
SPICE model; Pokaż więcej
Wydawca:: Warszawska Wyższa Szkoła Informatyki
Powiązania:: https://bibliotekanauki.pl/articles/91419.pdf Link otwiera się w nowym oknie
Opis:: In this paper piezoconductivity phenomenon in MOSFET channel is discussed and extension of drain current model with possibility of stress consideration is proposed. Analysis of obtained model combined with examination of stress components inherent in the MOSFET channel as well as distributions of specific piezoconductance coefficients on a plane of channel can show which directions of transistor channel are desirable for improvement of MOSFET performances. This model gives possibility to predict optimal transistor channel orientation, for the given stress state in MOSFET channel. Possible simplification of this model is considered. In particular, stress state and significant piezoconductance coefficient distributions on planes f100g, f110g as well as f111g are analyzed. For assumed particular cases of stress state in the channel, final models of MOSFT for considered specific planes are given.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 4.

Tytuł:: Recent developments in vertical MOSFETs and SiGe HBTs
Autorzy:: Hall, S.
Buiu, O.
Ashburn, P.
de Groot, K.
Tematy:: vertical MOSFET
HBT
SOI; Pokaż więcej
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Powiązania:: https://bibliotekanauki.pl/articles/308031.pdf Link otwiera się w nowym oknie
Opis:: There is a well recognised need to introduce new materials and device architectures to Si technology to achieve the objectives set by the international roadmap. This paper summarises our work in two areas: vertical MOSFETs, which can allow increased current drive per unit area of Si chip and SiGe HBT's in silicon-on-insulator technology, which bring together and promise to extend the very high frequency performance of SiGe HBT's with SOI-CMOS.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 5.

Tytuł:: Silicon microelectronics: where we have come from and where we are heading
Autorzy:: Łukasiak, L.
Jakubowski, A.
Pióro, Z.
Tematy:: MOSFET
scaling
SiGe
SOI; Pokaż więcej
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Powiązania:: https://bibliotekanauki.pl/articles/308029.pdf Link otwiera się w nowym oknie
Opis:: The paper briefly presents the history of microelectronics and the limitations of its further progress, as well as possible solutions. The discussion includes the consequences of the reduction of gate-stack capacitance and difficulties associated with supply-voltage scaling, minimization of parasitic resistance, increased channel doping and small size. Novel device architectures (e.g. SON, double-gate transistor) and the advantages of silicon-germanium are considered, too.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 6.

Tytuł:: Electron mobility and drain current in strained-Si MOSFET
Autorzy:: Walczak, J.
Majkusiak, B.
Tematy:: electron mobility
strained-Si MOSFET; Pokaż więcej
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Powiązania:: https://bibliotekanauki.pl/articles/308631.pdf Link otwiera się w nowym oknie
Opis:: Electron mobility and drain current in a strained-Si MOSFET have been calculated and compared with the mobility and drain current obtained for the relaxed material. In the first step, our mobility model has been calibrated to the "universal mobility" according to the available experimental data for unstrained Si MOSFETS. Then, employing the mobility parameters derived in the calibration process, electron mobility and the drain current have been calculated for strained-Si MOSFETs.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 7.

Tytuł:: Niskostratny drajwer tranzystora MOSFET mocy
Low Loss Power MOSFET Driver
Autorzy:: Legutko, P.
Tematy:: drajwer
straty mocy
czasy przełączeń
tranzystor MOSFET
driver
analysis
power losses
MOSFET transistor; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/155591.pdf Link otwiera się w nowym oknie
Opis:: W artykule przedstawiono nową konstrukcję dyskretnego drajwera dedykowanego do zastosowań z wysokoczęstotliwościowymi tranzystorami MOSFET mocy. Przedstawiono przebiegi czasowe oraz charakterystyki strat mocy zarówno drajwerów scalonych, jak i nowego dyskretnego układu. Opracowany dyskretny układ drajwera charakteryzuje się niskimi stratami mocy i krótszymi czasami przełączeń przy częstotliwości 30 MHz. Koszt opracowania nowego drajwera jest kilkakrotnie niższy niż koszt zakupu drajwera scalonego.
This paper presents a systematic approach to the design of high performance gate drive circuits for high speed switching applications. Two integrated drivers DEIC420, DEIC515 and additionally one discrete driver UCC27526 have been designed in the project. The UCC27526 driver was built with low-power discrete circuits connected in parallel by means of appropriate buffers reinforcement signal generator. Figure 1 shows the transistor gate circuit connected to the driver circuit. Figures 2 and 3 present the circuit driver UCC27526. Additionally, in this paper there are presents the characteristics of the driver input power (Fig. 4) for three operating states: a) no load; b) capacitance load 3 nF; c) loading with MOSFET gate. The output voltage waveforms for the DEIC420 and 8xUCC27526 drivers for three operating states are shown in Figures 5 and 6. The new MOSFET Drivers have been verified by use in the universal laboratory in the Department of Power Electronics, Electrical Drives and Robotics of Silesian University of Technology.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 8.

Tytuł:: Direct extraction techniques of microwave small-signal model and technological parameters for sub-quarter micron SOI MOSFETs
Autorzy:: Goffioul, M.
Vanhoenacker, D.
Raskin, J.P.
Tematy:: microelectronics
microwave devices
SOI MOSFET; Pokaż więcej
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Powiązania:: https://bibliotekanauki.pl/articles/309316.pdf Link otwiera się w nowym oknie
Opis:: Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 9.

Tytuł:: Comparison of microwave performances for sub-quarter micron fully- and partially-depleted SOI MOSFETs
Autorzy:: Goffioul, M.
Dambrine, G.
Vanhoenacker, D.
Raskin, J.P.
Tematy:: microelectronics
microwave devices
SOI MOSFET; Pokaż więcej
Wydawca:: Instytut Łączności - Państwowy Instytut Badawczy
Powiązania:: https://bibliotekanauki.pl/articles/309323.pdf Link otwiera się w nowym oknie
Opis:: The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lenghts and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 žm FD SOI n-MOSFETs with a total gate width of 100 žm present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for V(ds) = 0.75 V and P(dc) < 3 mW. A maximum extrapolated oscillation frequency of about 70 GHz has been obtained at V(ds) = 1 V and J(ds) = 100 mA/mm. This new generation of MOSFETs presents very good analogical and digital high speed performances with a low power consumption which make them extremely attractive for high frequency portable applications such as the wireless communications.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 10.

Tytuł:: Study of Capacitor & Diode Aging effects on Output Ripple in Voltage Regulators and Prognostic Detection of Failure
Autorzy:: K, Preethi Sharma
Vijayakumar, T
Tematy:: Buck
MOSFET
ESR
SMPS
voltage ripple; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/2055277.pdf Link otwiera się w nowym oknie
Opis:: Objectives: To design and simulate a buck converter and detector circuit which can prognostically indicate the power supply failure. Failure of Aluminium Electrolytic Capacitor (AEC) is considered as the parameter causing the power supply failure. To analyse variation of output ripple voltage due to possible changes in the Equivalent Series Resistance (ESR) and effective capacitance of the capacitor and design a detector to detect the failure of power supply prognostically. Methods: A DC-DC buck converter in SMPS topology is designed by assuming an input voltage of 12V with 3 volts possible fluctuations and an output voltage of 3.3 volts is desired. Simulation is carried out to measure the variation in output ripple voltage caused due to aging of electrolytic capacitor using TINA by Texas Instruments. A detector is also designed to compare the ripple voltage and a predefined threshold voltage so as to indicate the possible failure of Switched Mode Power Supply (SMPS) well in advance by monitoring the output ripple increase. Novelty: Having a fault tolerant power supply is very important in safety critical applications. Here by monitoring the output ripple variation, the degradation of AEC is predicted by calculating the ESR and capacitance variation. This simple yet effective prognostic detection will support in the design of fault tolerant power supplies. Highlight: It is found that, the ripple at the output increases with aging of the electrolytic capacitor, as with time the equivalent capacitance decreases and Equivalent Series Resistance (ESR) of the capacitor increases. The designed detector output is found to prognostically indicate the failure of SMPS.
Dostawca treści:: Biblioteka Nauki

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