- Tytuł:
- Hardware Accelerated Simulation of Crest Factor Reduction Block for Mobile Telecommunications
- Autorzy:
-
Nikodem, M.
Kępa, K. - Tematy:
-
crest factor reduction
configurable hardware
hardware acceleration
FPGA
telecommunications - Pokaż więcej
- Wydawca:
- Polska Akademia Nauk. Czytelnia Czasopism PAN
- Powiązania:
- https://bibliotekanauki.pl/articles/226366.pdf Link otwiera się w nowym oknie
- Opis:
- This paper reports results of the hardware accelerated simulations of the crest factor reduction (CFR) block which is a common element of the radio signal processing path in base stations for mobile telecommunications. Presented approach increases productivity of radio system architects by shortening the time of model architecture evaluation. This enables unprecedented scale of CFR parameter optimization which requires thousands of simulation runs. We use FPGA device and Xilinx System Generator for DSP technology in order to model CFR block in MATLAB/Simulink environment, implement the accelerator and use it for mixed hardware-software simulation. Reported approach reduces simulation time by 70%, provides straight forward use of fixed-point arithmetic and lowers power consumption by 73% at the cost of constant and relatively low overhead on model development.
- Dostawca treści:
- Biblioteka Nauki
Artykuł