Temat: embedded design - Prolib Integro

Skocz do pozycji: 1.

Tytuł:: A New Design of a Robot Prototype for Intelligent Navigation and Parallel Parking
Autorzy:: Abdelmoula, Ch.
Chaari, F.
Masmoudi, M.
Tematy:: autonomous vehicles
embedded design
mobile robot; Pokaż więcej
Wydawca:: Sieć Badawcza Łukasiewicz - Przemysłowy Instytut Automatyki i Pomiarów
Powiązania:: https://bibliotekanauki.pl/articles/385043.pdf Link otwiera się w nowym oknie
Opis:: Nowadays, the design of industrial vehicles and movable cars is based on the automation of their different tasks, which are currently handled by humans. These tasks, such as maneuvering robots in complex environments, require high level of precision that cannot be guaranteed by humans. Manual operations are likely to produce errors of computation and optimization of navigation and manoeuvre (left, right, veering…). In this paper, a novel prototype of a well-structured robot for intelligent navigation and parallel parking applications is presented. The robot have two axels, the front one is composed of two wheels that are manoeuvred by a stepper motor, and a pinion rack system for controlling the rotation of the wheels, and also the orientation of the robot. The driving wheels are mounted in the rear axle of the robot and are commanded by two DC motors. The design allows modification of the robot structural components whenever required. In addition to the mechanical components, the prototype is equipped with a DC power supply, three infra-red sensors, one ultrasound sensor, and control modules composed of an FPGA card, microcontroller card and two cards which are responsible for commanding actuators. The parameters of the mechanical and electronics components are optimised to perform multiple tasks for training and instruction applications. A mathematical model that describes the dynamics of the robot prototype is also developed. Simulation, experimental and theoretical investigations were carried out consisting in navigation and parallel parking manoeuvres. It was confirmed that the experimental and theoretical results agree well in both applications.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 2.

Tytuł:: Assignment of unexpected tasks for a group of embedded systems
Autorzy:: Ogorzałek, Maciej
Górski, Adam
Opis:: Unexpected tasks can appear when an embedded system has been designed and is operating in a defined structure. In such a situation it is not possible to add any new component to the system. In some situations modification of the architecture is possible to be made but cost of such an operation can be very high and not economically justified. In such a situation some of unexpected tasks cannot be executed by the system. Cooperation of two or more embedded systems could possibly solve such a problem. Two or more cooperating embedded systems can even execute some tasks that cannot be executed separately by one individual system. Therefore we believe that that it is very important to provide methodologies to assign to a group of embedded systems unexpected tasks that cannot be executed separately by any system by itself.
Dostawca treści:: Repozytorium Uniwersytetu Jagiellońskiego

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Skocz do pozycji: 3.

Tytuł:: GP-based methodology for HW/SW co-synthesis of multiprocessor embedded systems with increasing number of individuals obtained by mutation
Autorzy:: Górski, Adam
Ogorzałek, Maciej
Wydawca:: SciTePress
Opis:: In this work, a genetic programming methodology for co-synthesis of multiprocessor systems is presented. Genotype is a tree which nodes include system construction procedures. Thus the design methodology is evolving. Next generations are obtained using genetic operators: mutation, reproduction and crossover. Unlike other algorithms in presented methodology number of individuals obtained by mutation operator is not const. Therefore number of individuals in each population is increasing. The size of final generation is found by the algorithm.
Dostawca treści:: Repozytorium Uniwersytetu Jagiellońskiego

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Skocz do pozycji: 4.

Tytuł:: Iterative improvement methodology for hardware/software co-synthesis of embedded systems using genetic programming
Autorzy:: Górski, Adam
Ogorzałek, Maciej
Wydawca:: Institute of Electrical and Electronics Engineers (IEEE)
Opis:: In this paper we present a novel developmental genetic programming methodology for co-synthesis of distributed embedded systems. This methodology is based on iterative improvement algorithms. Genotype is represented by a tree. Unlike existing genetic programming approaches, our methodology starts from the fastest architecture. Every node in the tree is a chromosome and describes system refinement option. Thus the co-synthesis process is evolving. Using genetic operators: crossover, mutation and selection new systems are created.
Dostawca treści:: Repozytorium Uniwersytetu Jagiellońskiego

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Skocz do pozycji: 5.

Tytuł:: Assignment of unexpected tasks in embedded system design process
Autorzy:: Ogorzałek, Maciej
Górski, Adam
Opis:: Embedded systems design process focuses on three areas: modeling, validation and implementation. Typically such procedure assumes constant number of tasks in every instance of designing procedure. Thus the designer must predict all possible tasks executed by the system. Serious problems appear when the system has to execute unexpected tasks. In this case the design process must be repeated. We propose a new approach in embedded system design process which covers such situation. In the approach unexpected tasks are assigned to previously allocated resources. Therefore the system can execute more tasks that were predicted by the designer.
Dostawca treści:: Repozytorium Uniwersytetu Jagiellońskiego

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Skocz do pozycji: 6.

Tytuł:: Adaptive GP-based algorithm for hardware/software co-design of distributed embedded systems
Autorzy:: Górski, Adam
Ogorzałek, Maciej
Wydawca:: SciTePress
Opis:: In this work, a novel adaptive approach to co-design of embedded systems is presented. The approach is based on developmental genetic programming. Unlike most of existing algorithms, presented methodology involves evolving co-synthesis process, not the system architecture directly. Genotype is a tree which nodes include system construction options. The system can adapt to the environment by increasing chromosomes which give better results in each situations. Half of the next populations is created using genetic operators (crossover, mutation, reproduction). Second half is obtained by generating additional solutions but with different probability of the options.
Dostawca treści:: Repozytorium Uniwersytetu Jagiellońskiego

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Skocz do pozycji: 7.

Tytuł:: Testowanie układów cyfrowych z wykorzystaniem magistrali IEEE 1149.7
Fault detection in digital circuits using IEEE 1149.7 test bus
Autorzy:: Bartosiński, B.
Tematy:: projektowanie ułatwiające testowanie
systemy wbudowane
magistrala testująca
IEEE 1149.7
Design for Testability
embedded systems; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/153720.pdf Link otwiera się w nowym oknie
Opis:: Przedstawiono opracowaną w grudniu 2009 r. cyfrową magistralę testującą IEEE 1149.7 przeznaczoną do testowania i debuggingu wielordzeniowych układów wbudowanych. W stosunku do magistrali IEEE1149.1, której jest rozszerzeniem, magistrala IEEE1149.7 zapewnia zredukowaną do dwóch liczbę wyprowadzeń, możliwość pracy w konfiguracji gwiazdowej, indywidualne adresowanie urządzeń, eliminację ze ścieżki brzegowej nieaktywnych układów, zarządzanie zasilaniem oraz rozszerzone możliwości debugingu oprogramowania układów mikroprocesorowych.
The IEEE 1149.7 bus developed in December 2009, designed for testing and debugging of multi-core embedded circuits is presented in the paper. The IEEE 1149.7 bus is based on the idea of a boundary scan path and constitutes an extension of the testing bus IEEE 1149.1 widely used in industry [1] (Fig. 1). The properties of the IEEE 1149.7 [5] belong to classes T0-T5 (Fig. 2). Class T0 (Compliant Class) ensures compatibility with Standard IEEE 1149.1. Classes T1-T3 (Extended Classes) expand the possibilities of the IEEE 1149.7 Standard, whereas Classes T4-T5 (Advanced Classes) add new possibilities connected with two wire operation. In relation to the IEEE 1149.1 Standard, the IEEE49.7 bus provides the ability to quickly access a specific device in a system with multiple devices (Fig. 6), operation in a star topology (Fig. 7), reduced to 2 number of pin (Fig. 8), power management and extended possibilities of debugging microprocessor software. These properties facilitate considerably the testing of embedded SOC circuits and stacked die devices with many semiconductor structures in one IC package. The enhanced functionality and reduced number of pin in the IEEE 1149.7 do not interfere with co-operation with IEEE 1149.1 circuits, which allows going on with testing the earlier-developed procedures and infrastructure for IEEE 1149.1. It is expected that in the near future the IEEE 1149.7 bus will find even more support, as IEEE 1149.1, by the industry.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 8.

Tytuł:: Assignment of unexpected tasks in embedded system design process
Autorzy:: Górski, Adam
Ogorzałek, Maciej
Opis:: Embedded systems design process focuses on three areas: modeling, validation and implementation. Typically such procedure assumes constant number of tasks in every instance of designing procedure. Thus the designer must predict all possible tasks executed by the system. Serious problems appear when the system has to execute unexpected tasks. In this case the design process must be repeated. We propose a new approach in embedded system design process which covers such situation. In the approach unexpected tasks are assigned to previously allocated resources. Therefore the system can execute more tasks that were predicted by the designer.
Dostawca treści:: Repozytorium Uniwersytetu Jagiellońskiego

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Skocz do pozycji: 9.

Tytuł:: Synteza automatu Moore’a z wbudowanym blokiem pamięci w strukturach programowalnych
EMB-based synthesis of Moore FSM
Autorzy:: Kołopieńczyk, M.
Barkalov, A.
Titarenko, L.
Tematy:: Moore FSM
RAM
wbudowane bloki pamięci
projektowanie
układy logiczne
Mealy FSM
FPGA
Embedded Memory Block
design
logic circuit; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/972136.pdf Link otwiera się w nowym oknie
Opis:: W artykule zostanie przedstawiona metoda umożliwiająca syntezę skończonego automatu stanów typu Moore’a z wbudowanym blokiem pamięci (ang. Embedded Memory Blocks, EMB) w strukturach programowalnych typu FPGA (ang. Field Programmable Gate Array, FPGA). Zaproponowana metoda bazuje na kodowaniu pewnej wybranej części zbioru warunków logicznych przez dodatkowe zmienne. W artykule zostanie zaprezentowany przykład projektowania układu.
The model of the Moore finite state machine (FSM) is very often used for representing a control unit [1]. Nowadays, two classes of programmable logic devices: complex programmable logic devices (CPLD) and field-programmable gate arrays (FPGA) are used for implementing logic circuits of FSMs [2, 3]. This paper deals with FPGA-based Moore FSMs. It is very important to use EMBs in the logic design. It leads to decreasing in both the number of interconnections and chip area occupied by an FSM logic circuit. In turn, it results in decrease in the propagation time as well as the consumed power of a circuit [9]. A lot of methods for implementing an FSM logic circuit with RAMs are known [10 – 19]. For rather complex FSMs, the method of replacement of logical conditions [20] is used. In this case, optimization efforts target hardware reduction for the multiplexer executing the replacement. In this paper we propose a method based on existence of pseudoequivalent states of the Moore FSM for solving this problem [21]. The method is based on replacement of some part of the set of logical conditions by additional variables. It results in diminishing the number of LUTs in the multiplexer used for replacement of logical conditions. To represent a control algorithm, the language of graph-schemes of algorithms [20] is used. An example of application of the proposed design method is given.
Dostawca treści:: Biblioteka Nauki

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Skocz do pozycji: 10.

Tytuł:: Embedded control system development for the solution of self-adjusted regulator design problem and its robustness properties estimation
Autorzy:: Zamyatin, S. V.
Kurgankin, V. V.
Rudnicki, V. A.
Tematy:: automatic control system
embedded system
regulator design
dynamic compensation principle
robustness
real interpolation method
discrete real Laplace transformation; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/199963.pdf Link otwiera się w nowym oknie
Opis:: The possibility of the embedded automatic-control system construction for a self-adjusted regulator design on the basis of dynamic compensation principle is observed. The description of mathematical and algorithmic apparatus of Control Object identification in a digital form resulted in a design of the regulator. Results of natural experiments are given. An analysis of the regulator robustness properties is carried out.
Dostawca treści:: Biblioteka Nauki

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