Temat: field programmable gate array (FPGA)

Skocz do pozycji: 1.

Tytuł:: Pulse Sequence Shaper For Radiospectroscopy And Relaxation Methods In NQR
Autorzy:: Bobalo, Y.
Hotra, Z.
Hotra, O.
Politans’kyy, L.
Samila, A.
Tematy:: NQR
pulse sequence
field programmable gate array (FPGA)
frequency synthesizer; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/221794.pdf Link otwiera się w nowym oknie
Opis:: A pulse sequence shaper for the pursuance of the research using a wide spectrum of radiospectroscopy and relaxation methods in NQR is proposed. The distinctive feature of this product is its implementation with the application of a multi-functional programmable frequency synthesizer suitable for high-speed amplitude and phase manipulations.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 2.

Tytuł:: An efficient hardware implementation of a combinations generator
Autorzy:: Mazurkiewicz, T.
Tematy:: information technology
generator of combinations
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Uniwersytet Warmińsko-Mazurski w Olsztynie
Powiązania:: https://bibliotekanauki.pl/articles/298447.pdf Link otwiera się w nowym oknie
Opis:: In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 3.

Tytuł:: Zmiennoprzecinkowa jednostka arytmetyczna dla sprzętowej maszyny wirtualnej
A floating point unit for the hardware virtual machine
Autorzy:: Hajduk, Z.
Tematy:: układy FPGA
arytmetyka zmiennoprzecinkowa
field programmable gate array (FPGA)
floating point arithmetic; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/156437.pdf Link otwiera się w nowym oknie
Opis:: W artykule omówiono, opracowaną dla struktur FPGA, implementację układów realizujących podstawowe operacje arytmetyki zmiennoprzecinkowej. Implementacja charakteryzuje się pewnym kompromisem pomiędzy zapotrzebowaniem na zasoby logiczne układu programowalnego a szybkością realizacji operacji arytmetycznych określoną przez liczbę taktów zegara niezbędną do wykonania operacji. Wspomniane układy zostały wykorzystane jako zasadnicze komponenty zmiennoprzecinkowej jednostki arytmetycznej przeznaczonej dla sprzętowej maszyny wirtualnej. Maszyna ta, implementowana w układach FPGA, jest specjalizowanym mikrokontrolerem wykonującym pośredni kod wykonywalny generowany przez kompilator środowiska inżynierskiego CPDev, przeznaczonego do projektowania oprogramowania sterowników przemysłowych. Wykonane testy wydajności maszyny sprzętowej wyposażonej w zmiennoprzecinkową jednostkę arytmetyczną wskazują, że jest ona średnio kilkadziesiąt razy szybsza od dotychczas istniejących realizacji programowych, wykorzystujących popularne mikrokontrolery AVR i ARM.
Under the CPDev (Control Program Developer) engineering environment, programs written in one of the languages defined in the IEC 61131-3 standard are compiled into the universal intermediate code executed on the side of programmable controllers by the virtual machines [9]. There are software implemented virtual machines, dedicated for the platform with popular AVR and ARM microcontrollers, and also there is a recently developed hardware virtual machine implemented using FPGA devices [2]. The hardware virtual machine, which in fact is a specialized microcontroller described in the Verilog Hardware Description Language [3], is several dozen times faster then its software counterparts [2]. But the main drawback of the existing hardware virtual machine is a lack of the ability of executing the floating point computations. The paper presents an architecture of the floating point arithmetic unit accomplishing basic floating point operation, designed for the hardware virtual machine. There are quite a lot of publications concerning FPGA implementation of the floating point arithmetic, for instance [6, 7, 8, 10, 11]. In this paper the realization of basic float-ing point operation, balanced between logic resources requirements and speed of computing (defined by the number of clock cycles necessary to end up a floating point operation), is presented. Figs. 1 and 2 show a simplified micro-architecture of the single precision (according to IEEE 754-1985 standard [5]) floating point multiplier and adder. A floating point divider has roughly the same structure as the multiplier - it differs in states functions performed by some blocks. A few different realizations of the multiplier and adder unit were designed - the details are presented in Tabs. 1 and 3. The general trend is as follows: a shorter clock cycle necessary to execute the operation needs more logic resources of FPGA. A floating point unit for the hardware virtual machine was designed based on the floating point multiplier, divider and adder blocks. Apart from the mentioned above basic floating point operation, the floating point unit also performs operations like: comparison and relation (equals, not equals, more than, more than or equal etc.), absolute value, negation, integer value to floating point value conversion, floating point to integer conversion (rounding, truncating) and some functions fetched from IEC 61131-3 standard like MIN, MAX, LIMIT. To compare performance of the hardware virtual machine equipped with the floating point unit and its software counterparts, the Whetstone based benchmark [1] was written in ST language. The test results are given in Tab. 4. The hardware virtual machine (implemented using Xilinx Spartan 3-AN FPGA XC3S1400AN-4FGG676) is several times faster than the software one implemented on AVR and ARM microcontrollers, and even a little bit faster than the PC based virtual machine (under .NET environment).
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 4.

Tytuł:: Synthesis of FSMs Based on Architectural Decomposition with Joined Multiple Encoding
Autorzy:: Bukowiec, A.
Tematy:: Boolean algebra
circuit synthesis
field programmable gate array (FPGA)
sequential circuits; Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/227248.pdf Link otwiera się w nowym oknie
Opis:: The method of synthesis of the logic circuit of finite state machine (FSM) with Mealy's outputs is proposed in this paper. Proposed method is based on the innovate encoding of microinstructions split into subsets. Code of microinstruction is represented as a part of current state code and code of microinstruction inside of current subset. It leads to realization of FSM as s double-level structure. It leads to diminishing of number of variables required for encoding of microinstructions. Such approach permits to decrease the number of required outputs of combinational part of FSM.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 5.

Tytuł:: Projekt i implementacja sterowników karty graficznej VGA w układach FPGA
Design and implementation of VGA graphics card in FPGA technology
Autorzy:: Niemojewski, M.
Sapiecha, P.
Tematy:: VGA
Video Graphics Adapter
FPGA
field-programmable gate array
Altera
Stratix II
Lancelot VGA
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/155616.pdf Link otwiera się w nowym oknie
Opis:: Celem pracy jest zaprojektowanie interfejsu graficznego i tekstowego umożliwiającego prezentacje informacji na ekranie monitora VGA wykorzystując technologie logicznych układów programowalnych, napisanie sterowników sprzętu dla systemu operacyjnego žClinux oraz przeprowadzenie i analiza wyników testów uzyskanego rozwiązania ze względu na parametry: prędkość rysowania obrazu, stopień obciążenia pamięci.
The paper presents design and implementation of the text and graphics interface for FPGA based system. The article describes VHDL module and video graphics driver for žClinux operating system. The article describes tests of the device. The paper presents possible future work for the design.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 6.

Tytuł:: A Random Number Generator Using Ring Oscillators and SHA-256 as Post-Processing
Autorzy:: Łoza, S.
Matuszewski, Ł.
Jessa, M.
Tematy:: random numbers
cryptography
ring oscillators
hash functions
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/963943.pdf Link otwiera się w nowym oknie
Opis:: Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called postprocessing. In this paper the hash function SHA-256 as postprocessing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 7.

Tytuł:: Digital random bit generators implemented in FPGAs offered by various manufacturers
Autorzy:: Kubczak, P.
Matuszewski, Ł.
Jessa, M.
Łoza, S.
Tematy:: true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/114475.pdf Link otwiera się w nowym oknie
Opis:: In cryptography, we require that a random sequence should have excellent statistical properties as well as non-deterministic character. Combining multiple independent sources of randomness using the modulo two operation, significantly improves the statistical properties of the generated sequences and also affects the accumulation of true randomness generated in the oscillator sources. This is a very promising method of producing random sequences. In this paper, we compare the implementations of the RO-based combined random generator in various FPGAs technologies offered by various manufactures (Xilinx, Altera, Lattice). In this research, we used a NIST 800-22 statistical test suite to assess the statistical properties. The results show that the method of producing strings with a combined generator is the method stable in terms of technology. The results are similar for implementation in all FPGA used in the experiment. So, the proposed generator can be implemented in various programmable structures together with other components of a cryptographic system.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 8.

Tytuł:: Research and Medical Transcranial Doppler System
Autorzy:: Lewandowski, M.
Walczak, M.
Karwat, P.
Witek, B.
Karłowicz, P.
Tematy:: Doppler system
digital signal processing
hardware-software partitioning
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Polska Akademia Nauk. Czytelnia Czasopism PAN
Powiązania:: https://bibliotekanauki.pl/articles/177389.pdf Link otwiera się w nowym oknie
Opis:: A new ultrasound digital transcranial Doppler system (digiTDS) is introduced. The digiTDS enables diagnosis of intracranial vessels which are rather difficult to penetrate for standard systems. The device can display a color map of flow velocities (in time-depth domain) and a spectrogram of a Doppler signal obtained at particular depth. The system offers a multigate processing which allows to display a numer of spectrograms simultaneously and to reconstruct a flow velocity profile. The digital signal processing in digiTDS is partitioned between hardware and software parts. The hardware part (based on FPGA) executes a signal demodulation and reduces data stream. The software part (PC) performs the Doppler processing and display tasks. The hardware-software partitioning allowed to build a flexible Doppler platform at a relatively low cost. The digiTDS design fulfills all necessary medical standards being a new useful tool in the transcranial field as well as in heart velocimetry research.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 9.

Tytuł:: A proposal of output speed multiplication technique for true random number generators based on ring oscillators
Autorzy:: Matuszewski, Ł.
Kubczak, P.
Tematy:: true random number generator
ring oscillator
cryptography
field programmable gate array (FPGA)
restart mechanism; Pokaż więcej
Wydawca:: Stowarzyszenie Inżynierów i Techników Mechaników Polskich
Powiązania:: https://bibliotekanauki.pl/articles/114218.pdf Link otwiera się w nowym oknie
Opis:: Nowadays modern cryptographic systems require a tremendous amount of keys. Very fast random number generators (RNGs) are needed to produce those keys in the requested time, but what to do when a solution that is already in use reaches the maximum speed? The aim of the paper is to find the answer to this question. In addition, generated random numbers should not leave a cryptographic system, because according to the Kerckhoffs thesis, the security of the whole system should be based only on a key. The cryptographic system should be enclosed within a single chip. In order to check new ideas and prove them, there were used NIST 800-22 test suite and restarts mechanism. The basic concept of the generator built of ring oscillators is still the same; ring oscillators are combined by XOR gates tree. A single ring oscillator consists of inverter, latch and NAND. This kind of construction provides a tool to make synchronous start and stop of all oscillators and the restart mechanism technique is applied in this manner. The speed of generation was increased by using multiple parallel generator trees to generate instantly the whole n-bit word. The paper shows that reproduction of the base structure is not a simple method of increasing the speed of generator. Moreover, it is always important to carefully consider all new ideas, because even if the NIST statistical test suite is passed, there is a chance that the restart mechanism will show some correlations that can be used during attack on the system.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Skocz do pozycji: 10.

Tytuł:: FPGA realization of an improved alpha max plus beta min algorithm
Autorzy:: Czyżak, M.
Smyk, R.
Tematy:: square root computation
alpha max plus beta min algorithm
field programmable gate array (FPGA); Pokaż więcej
Wydawca:: Politechnika Poznańska. Wydawnictwo Politechniki Poznańskiej
Powiązania:: https://bibliotekanauki.pl/articles/376709.pdf Link otwiera się w nowym oknie
Opis:: The improved version of the alpha max plus beta min square-rooting algorithm and its realization in the Field Programmable Gate Array (FPGA) are presented. The algorithm computes the square root to calculate the approximate magnitude of a complex sample. It is especially useful for pipelined calculations in the DSP. The improved version allows to reduce the peak error from about 4% to 0.33%. This is attained by determination of the approximate ratio of arguments and adequate selection of algorithm coefficients. Four approximation regions are used and hence four sets of coefficients. Also a Xilinx FPGA implementation for 12-bit sign magnitude numbers is shown.
Dostawca treści:: Biblioteka Nauki

Artykuł

na półce

Informacja

Wyszukujesz frazę "field programmable gate array (FPGA)" wg kryterium: Temat